An integrated circuit may include a p-channel metal oxide semiconductor (PMOS) transistor with silicon-germanium (SiGe) epitaxial source/drain regions. An instance of the SiGe source/drain regions may abut field oxide formed by a shallow trench isolation (STI) process. The SiGe source/drain region may have a highly angled surface facet and a cavity between the silicon germanium epitaxial material and the dielectric material of the field oxide.
A gate structure may be located on the field oxide adjacent to the SiGe source/drain region so that dielectric spacer material on a lateral surface of the gate structure may extend into the cavity and down to the silicon germanium epitaxial material, reducing an area for metal silicide on the SiGe source/drain region. A contact disposed on the SiGe source/drain region may undesirably provide a high resistance connection to the PMOS transistor due to the reduced silicide area and possibly in combination with alignment tolerance of the contact to the source/drain region.